synthesis tools中文是什么意思

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中文翻译
造句

逻辑综合工具

synthesis n. (pl. -ses ) 综合，【化学】合成；【逻辑 ...
tool n. 1.工具，用具，器具；【机械工程】刀具；工具母机 ...
tools 装配工具
for synthesis 合成用
synthesis n. (pl. -ses ) 综合，【化学】合成；【逻辑学】综合(法)；【语言学】综合(性)；语词的合成；【医学】接合；【物理学】合成综合。
abrasive tools 研磨工具
advanced tools 高级工具（什么工具？我没觉出来）
air tools 风动工具; 气动工具
aligning tools 校准工具
alignment tools 校直工具
analysis tools 刀轨分析工具; 分析工具
analytic tools 分析工具
animation tools 动画工具
are tools location 手工备品仓
artisan’s tools 工匠工具
assembly tools 装配工具
authoring tools 条目项下，列出了制作工具; 著作工具
auxiliary tools 辅助仪表
bar tools 用具
bibliographic tools 目录工具书
bibliographical tools 查目工具, 资料检索工具
bit tools 刀具
blasting tools 爆破工具
bone tools 骨骼工具
bricklayers tools 泥瓦工工具

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例句与用法

High level synthesis tool can choose best scheme in a large design space
高级综合工具可以在很大的设计空间中选择最优的设计方案。
Automatic synthesis tool after validation can eliminate error because of manual work
采用经过验证的自动综合工具，可以消除大部分可能由人工带来的设计错误。
The program deriving dynamic equations runs in puj 800 , double cpu , 256 mb memory . the synthesis tool and cmos chip of xilinx company are applied to design the hardware
本文中的动力学方程推导程序是在p 800 ，双cpu ， 256兆内存的机器上运行的。硬件的设计是采用xilinx公司的综合工具与芯片实现的。
Lastly , we use the high level synthesis tool synplify to test the validity of the improving mcu . according to the synthesis result , the system clock reached about 66mhz
最后,采用synplicity公司的高层综合工具synplify对所设计的mcu进行了综合,综合结果验证了改进型mcu满足了要求,工作频率达到66mhz 。
We implement des algorithm and 1024 - bit rsa algorithm with verilog hdl , and simulate their fpga implementation with modisim synthesis tool . finally we test the correctness and performance of the implementation method
采用veriloghdl语言编程实现了des算法和1024位rsa算法,并在modelsim综合仿真工具中对算法的fpga实现方法进行了仿真,检验了算法实现方法正确性和性能。
The circuit is synthesized by synplify pro which is synplicity ' s synthesis tool and emulated by quartus ii which is altera ' s developing tool , which has proved the feasibility and correctness of the circuit
采用硬件描述语言vetilog编写了硬件电路程序，并使用synplicity的综合工具synplifypro和altera开发工具quartus对电路系统进行了综合与仿真验证，证明了硬件电路的可行性与正确性。
I described the principles - . characteristics > function ^ system structure and design flow of synthesis in detail o although synthesis tool does an excellent job of converting hdl to gates . the structure of the hdl may not allow tool to meet the designer - specified constraints and very likely to result in an increase in compile time . the startpoint for synthesis affects the quality of results after synthesis , thus , to attain good startpoint the paper presented a lot of coding styles
本文回顾了集成电路设计方法学的发展，提出了它们的共同点是基于综合的设计思想，详细地介绍了综合的基本原理、特点、作用、综合的系统结构及设计流程；同时，虽然各公司提供的综合工具能很好地进行从hdl级的描述到门级的转换，但是hdl的结构有时会导致综合的结果难以满足预先的要求和综合时间的增加，所以hdl的编码风格对综合结果的影响很大。
Gae is basically a browser - server argumentation system , which supports loosely coupled group ' s activities , including group thinking and group decision modules , called knowledge creation tool and knowledge synthesis tool respectively . knowledge creation tool supports experts divergent thinking and qualitatively analyzing complex problems
基于web的b / s结构的松散耦合的gae系统给用户提供一个集约化知识支持平台，系统包括支持群思考和群决策的两个模块，分别是知识创造的发散工具和知识综合的收敛工具。
The characteristic of this ba is applying the dual scaling method to visualize the experts " argumentation contents , which can encourage participation , facilitate users assimilate others ideas , and stimulate emergence of more creative ideas . knowledge synthesis tool applies the ahp and ngt method , which are convergent method , to quantitatively testify the structure problems . in a word , gae system is an environment for solving complex problems
发散工具是专家发散思考，定性分析复杂问题的“场” ，特点是应用双尺度法( dualscalingmethod )将专家研讨内容加以可视化分析，这种二维图的表现形式刺激了专家进一步思考，拓宽其思维，帮助他们多视点、多角度、多侧面去了解所要解决问题的目标。
This design for mvbc system adopts top - down eda common design flow . circuit design adopts veriloghdl coding description . function simulation and timing verification adopt simulation tool vcs of synopsys inc , the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc , and the fpga advice stratix ii ep2s15
该mvbc系统设计采用业界通用的自上而下的eda设计方法,电路逻辑实现采用veriloghdl硬件语言描述,功能和时序验证的动态仿真采用synopsys公司的vcs ,而逻辑综合与fpga实现采用altera公司的集成开发环境quartusii软件以及stratixiiep2s15的fpga器件。